MMA685X datasheet(47/52 Pages) FREESCALE

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Freescale Semiconductor, Inc.

MMA685x

4.5.1

SPI Error

The following SPI conditions result in a SPI error:

• SCLK is high when CS is asserted

• the number of SCLK rising edges detected while CS is asserted is not equal to 16

• SCLK is high when CS is negated

• Command message parity error (MOSI)

• Bit 15 of Acceleration Data Request is not equal to ‘0’

• Bits 3 through 11 of an Acceleration Request are not equal to ‘0’

• Bits 0 through 7 of a Register Read Request are not equal to ‘0’

MMA685x responds to a SPI error with a “SPI Error” response as shown in Table 27. This applies to both acceleration data

request SPI errors, and Register Access SPI errors.

The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error.

4.5.2

SPI Data Output Verification Error

MMA685x includes a function to verify the integrity of the data output to the MISO pin. The function reads the data transmitted

on the MISO pin and compares it against the data intended to be transmitted. If any one bit doesn’t match, a SPI MISO Mismatch

Fault is detected and the MISOERR flag in the DEVSTAT register is set.

If a valid SPI acceleration request message is received during the SPI transfer with the MISO mismatch failure, the SPI accel-

eration request message is ignored and MMA685x responds with a “MISO Error” response during the subsequent SPI message

(reference Table 27). The Arming function is not updated if a MISO mismatch failure occurs. The PCM function is not affected by

the MISO mismatch failure.

If a valid SPI register write request message is received during the SPI transfer with the MISO mismatch failure, the register

write is completed as requested, but MMA685x responds with a “MISO Error” response as shown in Table 27, during the subse-

quent SPI message.

If a valid SPI register read request message is received during the SPI transfer with the MISO mismatch failure, the register

read is ignored and MMA685x responds with a “MISO Error” response as shown in Table 27, during the subsequent SPI mes-

sage. If the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared.

In all cases, the MISOERR flag in the DEVSTAT register will remain set until a successful SPI Register Read Request of the

DEVSTAT register is completed.

Figure 34. SPI Data Output Verification

4.5.3

Invalid Requests

4.5.3.1

Invalid Acceleration Request

The following conditions result in an “Invalid Acceleration Request” error:

• The Axis Selection bit (AX) in the Command message is set

• The SPI “Acceleration Data Request” Command data listed in Section 4.3, Table 29 does not match the internal

MMA685x responds to an “Invalid Acceleration Request” error with an “Invalid Accel Request” response as specified in

Table 27 on the subsequent SPI message only. No internal fault is recorded. The arming function will not be updated if an “Ac-

celeration Data Request Mismatch” Error is detected. The PCM output is not affected by the “Acceleration Data Request Mis-

match” error.

SCLK

SPI DATA OUT SHIFT REGISTER

DATA OUT BUFFER

MISO

MISO ERR

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