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MMA685X bảng dữ liệu(PDF) 25 Page - Freescale Semiconductor, Inc |
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MMA685X bảng dữ liệu(HTML) 25 Page - Freescale Semiconductor, Inc |
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25 / 52 page ![]() Sensors Freescale Semiconductor, Inc. 25 MMA685x 3.8.1 DSP Clock The DSP is clocked at 8 MHz, with an effective 6MHz operating frequency. The clock to the DSP is disabled for 1 clock prior to each edge of the ΣΔ modulator clock to minimize noise during data conversion. The bit streams from the two ΣΔ converters are processed through independent data paths within the DSP. Figure 12. Clock Generation 3.8.2 Decimation Sinc Filter The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 8 or 16, depending on the Low Pass Filter selected. Figure 13. Sinc Filter Response, tS = 8 μs 8 MHz OSC 6 MHz Digital 1MHz Modulator Hz () 1z 16 – – 16 1 z 1 – – () × ------------------------------------- 3 = |
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