MMA685X datasheet(34/52 Pages) FREESCALE

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Freescale Semiconductor, Inc.

MMA685x

3.8.7

Data Interpolation

MMA685x includes 2 to 1 data interpolation to minimize the system sample jitter. Each result produced by the digital signal

processing chain is delayed one half of a sample time, and the interpolated value of successive samples is provided between

sample times. This operation is illustrated in Figure 21.

Figure 21. Data Interpolation Timing

The effect of this interpolation at the system level is a 50% reduction in sample jitter. Figure 22 shows the resulting output data

for an input signal.

Figure 22. Data Interpolation Example

Sn-3

Sn-2

Sn-1

Sn-2

–

--------------------------------

–

--------------------------------

–

-------------------------

Sn-3

Response to SPI acceleration request occurring in this window receives interpolated sample

Response to SPI acceleration request occurring in this window receives true sample.

Internal Sample Rate

Output Sample Rate

Time

Input Signal

Internally Sampled Signal

Interpolated Samples

Internally

Sampled Values

Earliest Transmission

Point of Interpolated

Values

Earliest Transmission

Point of Internally

Sampled Values

Window of

Transmission for

Sampled Values

(Maximum: tS / 2)

Window of

Transmission for

Interpolated Values

(Maximum: tS / 2)

Fixed Latency:

tS / 2

= Signal Jitter =

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