ADSP-BF607 datasheet(33/44 Pages) AD

33 / 44 page

Preliminary Technical Data

Rev. PrD

Page 33 of 44

March 2012

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Typical

Max

Unit

VOH

High Level Output Voltage

VDD_EXT = 1.7 V, IOH = –0.5 mA

TBD

VOH

High Level Output Voltage

VDD_EXT = 3.13 V, IOH = –0.5 mA

TBD

VOL

Low Level Output Voltage

VDD_EXT = 1.7 V/3.13 V,

IOL = 2.0 mA

TBD

VOLTWI

1 Applies to bidirectional pins TWI_SCL and TWI_SDA.

Low Level Output Voltage

VDD_EXT = 1.7 V/3.13 V, IOL =2.0 mA

TBD

IIH

2 Applies to input pins.

High Level Input Current

VDD_EXT =3.47 V, VIN = 3.47 V

TBD

μA

IIL

Low Level Input Current

VDD_EXT =3.47 V, VIN = 0 V

TBD

μA

IIHP

3 Applies to JTAG input pins (JTG_TCK, JTG_TDI, JTG_TMS, JTG_TRST).

High Level Input Current JTAG

VDD_EXT = 3.47 V, VIN = 3.47 V

TBD

μA

IOZH

4 Applies to three-statable pins.

Three-State Leakage Current

VDD_EXT = 3.47 V, VIN = 3.47 V

TBD

μA

IOZHTWI

Three-State Leakage Current

VDD_EXT =3.13 V, VIN = 5.5 V

TBD

μA

IOZL

Three-State Leakage Current

VDD_EXT = 3.47 V, VIN = 0 V

TBD

μA

CIN

5, 6

5 Guaranteed, but not tested.

6 Applies to all signal pins.

Input Capacitance

fIN = 1 MHz, TAMBIENT = 25°C,

VIN =2.5 V

TBD

IDD_DEEPSLEEP

7 See the ADSP-BF60x Blackfin Processor Hardware Reference Manual for definition of deep sleep and hibernate operating modes.

VDD_INT Current in Deep Sleep Mode TBD

TBD

IDD_IDLE

VDD_INT Current in Idle

TBD

IDD_TYP

VDD_INT Current

TBD

IDD_HIBERNATE

7, 8

8 Applies to TBD supply pins only. Clock inputs are tied high or low.

Hibernate State Current

TBD

μA

IDD_DEEPSLEEP

VDD_INT Current in Deep Sleep Mode TBD

TBD

IDD_INT

VDD_INT Current

TBD

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