ADSP-BF607 datasheet(32/44 Pages) AD

32 / 44 page

Rev. PrD

Page 32 of 44

March 2012

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Preliminary Technical Data

Clock Related Operating Conditions

Table 9 describes the core clock timing requirements. The data

presented in the tables applies to all speed grades (found in

Automotive Products on Page 43) except where expressly noted.

Figure 8 provides a graphical representation of the various

clocks and their available divider values.

Table 9. Clock Operating Conditions

Parameter

Maximum

Unit

fCCLK

Core Clock Frequency (CCLK ≥ SYSCLK, CSEL ≤ SYSSEL)

TBD

MHz

fSYSCLK

SYSCLK Frequency (SYSSEL ≤ DSEL)

TBD

MHz

fSCLK0

1, 2

SCLK0 Frequency

TBD

MHz

fSCLK1

1, 2

SCLK1 Frequency

TBD

MHz

fDCLK

DDR2/LPDDR Clock Frequency

TBD

MHz

fOCLK

Output Clock Frequency

TBD

MHz

1 tSCLK0/1 is equal to 1/fSCLK0/1.

2 Rounded number. Actual test specification is a period of [TBD] ns.

Table 10. Phase-Locked Loop Operating Conditions

Parameter

Minimum

Maximum

Unit

fPLLCLK

PLL Clock Frequency

TBD

Speed Grade

MHz

Figure 8. Clock Relationships and Divider Values

CLKIN

PLL

DCLK

SYSCLK

CCLK

SCLK1

(SPORTS, SPI, ACM)

SCLK0

(PVP, ALL OTHER

PERIPHERALS)

CSEL

(1-32)

SYSSEL

(1-32)

S0SEL

(1-4)

S1SEL

(1-4)

DSEL

(1-32)

OCLK

OSEL

(1-128)

PLLCLK

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