R5F10RF8AFP datasheet(34/76 Pages) RENESAS

34 / 76 page

RL78/L12

2. ELECTRICAL SPECIFICATIONS (TARGET)

Page 34 of 73

R01DS0157EJ0001 Rev.0.01

2012.02.20

Under development

Preliminary document

Specifications in this document are tentative and subject to change.

Caution

The pins mounted depend on the product.

Refer to 1.3.1

32-pin products to 1.3.5

64-pin

products.

2.4 AC Characteristics

2.4.1 Basic operation

(TA =

−40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Items

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

≤ VDD ≤ 5.5 V 0.04167

μs

High-speed

main mode

2.4 V

≤ VDD < 2.7 V 0.0625

μs

Low voltage

main mode

1.6 V

≤ VDD ≤ 5.5 V

0.25

μs

Main

system

clock (fMAIN)

operation

Low-speed

main mode

1.8 V

≤ VDD ≤ 5.5 V 0.125

μs

Subsystem clock (fSUB)

operation

1.8 V

≤ VDD ≤ 5.5 V

28.5

30.5

31.3

μs

2.7 V

≤ VDD ≤ 5.5 V 0.04167

μs

High-speed

main mode

2.4 V

≤ VDD < 2.7 V 0.0625

μs

Low voltage

main mode

1.8 V

≤ VDD ≤ 5.5 V

0.25

μs

Instruction cycle (minimum

instruction execution time)

TCY

In the self

programming

mode

Low-speed

main mode

1.8 V

≤ VDD ≤ 5.5 V 0.125

μs

2.7 V

≤ VDD ≤ 5.5 V

1.0

20.0

MHz

1.8 V

≤ VDD < 2.7 V

1.0

8.0

MHz

fEX

1.6 V

≤ VDD < 1.8 V

1.0

4.0

MHz

External main system clock

frequency

fEXS

kHz

2.7 V

≤ VDD ≤ 5.5 V

1.8 V

≤ VDD < 2.7 V

tEXH, tEXL

1.6 V

≤ VDD < 1.8 V

120

External main system clock input

high-level width, low-level width

tEXHS, tEXLS

13.7

μs

TI00 to TI07 input high-level

width, low-level width

tTIH,

tTIL

1/fMCK+10

Note

4.0 V

≤ EVDD ≤ 5.5 V

MHz

2.7 V

≤ EVDD < 4.0 V

MHz

1.8 V

≤ EVDD < 2.7 V

MHz

High-speed main

mode

1.6 V

≤ EVDD < 1.8 V

MHz

Low voltage main

mode

1.6 V

≤ EVDD ≤ 5.5 V

MHz

1.8 V

≤ EVDD ≤ 5.5 V

MHz

TO00 to TO07 output frequency

fTO

Low-speed main

mode

1.6 V

≤ EVDD < 1.8 V

MHz

4.0 V

≤ EVDD ≤ 5.5 V

MHz

2.7 V

≤ EVDD < 4.0 V

MHz

1.8 V

≤ EVDD < 2.7 V

MHz

High-speed main

mode

1.6 V

≤ EVDD < 1.8 V

MHz

1.8 V

≤ EVDD ≤ 5.5 V

MHz

Low voltage main

mode

1.6 V

≤ EVDD < 1.8 V

MHz

1.8 V

≤ EVDD ≤ 5.5 V

MHz

PCLBUZ0, PCLBUZ1 output

frequency

fPCL

Low-speed main

mode

1.6 V

≤ EVDD < 1.8 V

MHz

INTP0

1.6 V

≤ VDD ≤ 5.5 V

μs

Interrupt input high-level width,

low-level width

tINTH,

tINTL

INTP1 to INTP7

1.6 V

≤ EVDD ≤ 5.5 V

μs

1.8 V

≤ EVDD ≤ 5.5 V

250

Key interrupt input low-level width tKR

KR0 to KR3

1.6 V

≤ EVDD < 1.8 V

μs

RESET low-level width

tRSL

μs

(Note and Remark are listed on the next page.)

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