TMX320LC2401AVFS datasheet(70/88 Pages) TI

70 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

LPM2 wake-up timing

switching characteristics over recommended operating conditions (see Figure 33)

PARAMETER

MIN

MAX

UNIT

td(PDP-PWM)HZ

Delay time, PDPINTA low to PWM

if bit 6 of SCSR2 = 0

(6 + 1)tc(CO) + 12†

td(PDP-PWM)HZ

Delay time, PDPINTA low to PWM

high-impedance state

if bit 6 of SCSR2 = 1

(12+ 1)tc(CO) + 12†

td(INT)

Delay time, INT low/high to interrupt-vector

fetch

10tc(CO) + tw(PDP−WAKE)

† Includes i/p qualifier cycles plus synchronization plus propagation delay

timing requirements (see Figure 33)

MIN

MAX

UNIT

tw(PDP−WAKE)

Pulse duration, PDPINTA input low

if bit 6 of SCSR2 = 0

6tc(CO)

tw(PDP−WAKE)

Pulse duration, PDPINTA input low

if bit 6 of SCSR2 = 1

12tc(CO)

PLL lock-up time

98 304tc(CI)

cycles

PWM

PDPINTA

CLKOUT‡§

tw(PDP−WAKE)

td(PDP-PWM)HZ

CPU Status

Interrupt Vector¶ or

Next Instruction#

td(INT)

XTAL1

Oscillator Disabled

CLKIN

tOSC†

CPU IDLE State (LPM2)

† tOSC is the oscillator start-up time.

‡ CLKOUT frequency after LPM2 wake-up will be the same as that upon entering LPM2 (x4 shown as an example).

§ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT

waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the

XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.

¶ PDPINTA interrupt vector, if PDPINTA interrupt is enabled.

# If PDPINTA interrupt is disabled.

Figure 33. LPM2 Wakeup Using PDPINTA

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