TMX320LC2401AVFS datasheet(41/88 Pages) TI

41 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

enhanced analog-to-digital converter (ADC) module

A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of

a 10-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:

D 10-bit ADC core with built-in S/H

D Fast conversion time (S/H + Conversion) of 500 ns

D 5-channel, MUXed inputs

D Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can

be programmed to select any 1 of 5 input channels

D Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer

(i.e., two cascaded 8-state sequencers)

D Sixteen result registers (individually addressable) to store conversion values

−

The digital value of the input analog voltage is derived by:

Digital Value

+ 1023

Input Analog Voltage

* V

REFLO

REFHI

* V

REFLO

NOTE: VREFLO is internally tied to VSSA; VREFHI is internally tied to VCCA.

D Multiple triggers as sources for the start-of-conversion (SOC) sequence

−

S/W − software immediate start

−

EVA − Event manager A (multiple event sources within EVA)

−

Ext − External pin (ADCSOC)

D Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS

D Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize

conversions

D EVA triggers can operate independently in dual-sequencer mode

D Sample-and-hold (S/H) acquisition time window has separate prescale control

NOTE: The 2401A ADC module is identical to the LF2407A ADC module. However, only channels ADCIN00

through ADCIN04 are bonded out of the device. For this reason, the valid values for the CONVnn bit fields in

the CHSELSEQn registers are from 0 to 4. Attempting to convert channels 5 through 15 would yield

indeterminate results.

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