PCF85176 datasheet(22/43 Pages) NXP

22 / 43 page

PCF85176_1

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Product data sheet

Rev. 01 — 14 April 2010

22 of 43

NXP Semiconductors

PCF85176

Universal LCD driver for low multiplex rates

• Up to 16 PCF85176 for very large LCD applications

• The use of two types of LCD multiplex drive

The I2C-bus protocol is shown in Figure 16. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of two possible PCF85176

slave addresses available. All PCF85176 whose SA0 inputs correspond to bit 0 of the

slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is

ignored by all PCF85176 whose SA0 inputs are set to the alternative level.

After an acknowledgement, one or more command bytes follow that define the status of

each addressed PCF85176.

The last command byte sent is identified by resetting its most significant bit, continuation

bit C (see Figure 17). The command bytes are also acknowledged by all addressed

PCF85176 on the bus.

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data directed to the intended PCF85176 device.

An acknowledgement after each byte is asserted only by the PCF85176 that are

addressed via address lines A0, A1, and A2. After the last display byte, the I2C-bus

master asserts a STOP condition (P). Alternately a START may be asserted to restart an

I2C-bus access.

Fig 16. I2C-bus protocol

Fig 17. Format of command byte

013aaa053

011100

0 A C

COMMAND

DISPLAY DATA

slave address

R/W

acknowledge by

all addressed

PCA85176s

acknowledge

by A0, A1 and A2

selected

PCA85176 only

1 byte

update data pointers

and if necessary,

subaddress counter

≥ 1 byte(s)

≥ 0 byte(s)

msa833

REST OF OPCODE

MSB

LSB

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