PIC32MX795F512LT-80ISLASHPF datasheet(95/256 Pages) MICROCHIP

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TABLE 4-22:

FLASH CONTROLLER REGISTER MAP

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

F400 NVMCON(1)

31:16

—

0000

15:0

WREN

WRERR

LVDERR

LVDSTAT

—

NVMOP<3:0>

0000

F410

NVMKEY

31:16

NVMKEY<31:0>

0000

15:0

0000

F420 NVMADDR(1)

31:16

NVMADDR<31:0>

0000

15:0

0000

F430 NVMDATA

31:16

NVMDATA<31:0>

0000

15:0

0000

F440

NVMSRC

ADDR

31:16

NVMSRCADDR<31:0>

0000

15:0

0000

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.

TABLE 4-23:

SYSTEM CONTROL REGISTER MAP(1,2)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

F000 OSCCON

31:16

—

PLLODIV<2:0>

FRCDIV<2:0>

—

SOSCRDY

—

PBDIV<1:0>

PLLMULT<2:0>

0000

15:0

—COSC<2:0>

—

NOSC<2:0>

CLKLOCK

ULOCK

SLOCK

SLPEN

UFRCEN

SOSCEN

OSWEN

0000

F010 OSCTUN

31:16

—

0000

15:0

—

TUN<5:0>

0000

0000 WDTCON

31:16

—

0000

15:0

—

SWDTPS<4:0>

—

WDTCLR 0000

F600

RCON

31:16

—

0000

15:0

—

CMR

VREGS

EXTR

SWR

—

WDTO

SLEEP

IDLE

BOR

POR

0000

F610 RSWRST

31:16

—

0000

15:0

—

—SWRST

0000

F230

SYSKEY

31:16

SYSKEY<31:0>

0000

15:0

0000

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.

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