PIC32MX795F512LT-80ISLASHPF datasheet(79/256 Pages) MICROCHIP

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5220

I2C5ADD

31:16

—

0000

15:0

—

ADD<9:0>

0000

5230

I2C5MSK

31:16

—

0000

15:0

—

MSK<9:0>

0000

5240

I2C5BRG

31:16

—

0000

15:0

—

Baud Rate Generator Register

0000

5250

I2C5TRN

31:16

—

0000

15:0

—

Transmit Register

0000

5260

I2C5RCV

31:16

—

0000

15:0

—

Receive Register

0000

5300

I2C1CON

31:16

—

0000

15:0

FRZ

SIDL

SCLREL

STRICT

A10M

DISSLW

SMEN

GCEN

STREN

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

1000

5310

I2C1STAT

31:16

—

0000

15:0 ACKSTAT

TRSTAT

—

BCL

GCSTAT

ADD10

IWCOL

I2COV

D/A

R/W

RBF

TBF

0000

5320

I2C3DD

31:16

—

0000

15:0

—

ADD<9:0>

0000

5330

I2C1MSK

31:16

—

0000

15:0

—

MSK<9:0>

0000

5340

I2C1BRG

31:16

—

0000

15:0

—

Baud Rate Generator Register

0000

5350

I2C1TRN

31:16

—

0000

15:0

—

Transmit Register

0000

5360

I2C1RCV

31:16

—

0000

15:0

—

Receive Register

0000

TABLE 4-11:

I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP(1) (CONTINUED)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”

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