IC-MPEVALMP1D datasheet(10/22 Pages) ICHAUS

10 / 22 page

iC-MP 8-BIT HALL ANGLE ENCODER

WITH RATIOMETRIC OUTPUT

Rev B1, Page 10/22

SERIAL OUTPUT (SLO)

Figure 6: Serial data timing

D0 to D7 make up the absolute position data with re-

spect to the programmed position offset (OFFSET1 xor

OFFSET2 xor OFFSET3).

The absolute position is latched by a low to high tran-

sition at MA (see T1).

After an acknowledge (T2) at SLO iC-MP requests pro-

cessing time until the start condition (T3) is sent. Pro-

cessing time must be provided in Slow Scanning Mode

during startup.

With rising edge T4 at the clock pin the most signiﬁcant

bit (D7) is placed on the serial data line SLO. After T5

has elapsed the controller can stop clocking at MA and

the device is ready to latch a new position after a time-

out (tout). If the controller continues to clock in a daisy

chain in Fast Scanning Mode after T5 has elapsed, the

second device (slave 2) outputs the position latched at

T1 at pin SLO.

The absolute position data (D0-D7) is binary coded.

The position data and the error bit (NERR) are CRC

protected. The CRC polynomial is X4+X+1 = 0x13.

Figure 7: Example CRC calculation

Figure 8: Timing in Fast Scanning Mode

Figure 9: Timing in Slow Scanning Mode

IC-MPEVALMP1D bảng dữ liệu(PDF) 10 Page - IC-Haus GmbH