WITH RATIOMETRIC OUTPUT

Rev B1, Page 7/22

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise stated

Item

Symbol

Parameter

Conditions

Unit

No.

Min.

Typ.

Max.

503

Vt1()hys

Threshold Hysteresis

Vt1()hys = Vt1()hi − Vt1()lo

230

400

mV

504

Vt2()hi

Voltage Threshold hi vs. VDD

Vt2()hi = V() - VDD,

VDD = 5 V ±5%, Tj = 10 ... 40 °C

1.3

V

505

Vt2()lo

Voltage Threshold lo vs. VDD

Vt2()lo = V() - VDD;

VDD = 5 V ±5%, Tj = 10 ... 40 °C

0.7

V

506

Vt2()hys

Threshold Hysteresis

Vt2()hys = Vt2()hi − Vt2()lo

20

150

mV

507

Vzap()

Permissible Zapping Voltage

VDD = 5 V ±5%, Tj = 10 ... 40 °C

7.3

7.4

7.5

V

508

Izap()

Required Zapping Current

VDD = 5 V ±5%, Tj = 10 ... 40 °C

90

mA

Serial Interface and Power Save Mode Inputs: MA, SLI, PSMI

601

Vt()hi

Input Threshold Voltage hi

2

V

602

Vt()lo

Input Threshold Voltage lo

0.8

V

603

Vt()hys

Input Hysteresis

Vt()hys = Vt()hi − Vt()lo

230

mV

604

Ipu()

Input Pull-up Current

V() = 0...VDD − 1 V

-240

-120

-10

µA

605

fclk(MA)

Permissible Clock Frequency at

MA

Normal mode

0.080

10

MHz

606

tzap(MA)

Permissible Zapping Cycle at MA Programming mode,

VDD = 5 V ±5%, Tj = 10 ... 40 °C

4.5

5

5.5

µs

607

tout(MA)

Interface Timeout

Time from MA last edge to SLO lo → hi

15

µs

Serial Interface and Power Save Mode Outputs: SLO, PSMO

701

Vs()hi

Saturation Voltage hi

Vs()hi = VDD − V(), I() = -4 mA

0.4

V

702

Vs()lo

Saturation Voltage lo

I() = 4 mA

0.4

V

703

Isc()hi

Short-Circuit Current hi

V() = 0 V

-90

-10

mA

704

Isc()lo

Short-Circuit Current lo

V() = VDD

10

90

mA

705

tr()

Rise Time

CL() = 50 pF, V(): 20 → 80%

60

ns

706

tf()

Fall Time

CL() = 50 pF, V(): 80 → 20%

60

ns

I/O Interface NERR

801

Vs()lo

Saturation Voltage lo

I() = 4 mA

0.4

V

802

Ilk()

Leakage Current

V() = 0...VDD, PSMI = hi

-5

5

µA

803

Isc()lo

Short-Circuit Current lo

V() = VDD

4.5

90

mA

Test Signals at NERR, LAO, PSMO (iC-Haus device test only)

902

VREF

Reference Voltage at LAO

Op. mode: Test 2

45

50

55

%VDD

904

Vpp(PSIN) Pos. Sine Sensor AC Signal

at NERR

Op. mode: Test 0

2

Vpp

905

Vdc(PSIN) Pos. Sine Sensor DC Signal

at NERR

Op. mode: Test 0

VREF

V

906

Vpp(PCOS) Pos. Cosine Sensor AC Signal

at LAO

Op. mode: Test 0

2

Vpp

907

Vdc(PCOS) Pos. Cosine Sensor DC Signal

at LAO

Op. mode: Test 0

VREF

V

908

Vpp(NSIN) Neg. Sine Sensor AC Signal

at NERR

Op. mode: Test 1

2

Vpp

909

Vdc(NSIN) Neg. Sine Sensor DC Signal

at NERR

Op. mode: Test 1

VREF

V

910

Vpp(NCOS) Neg. Cosine Sensor AC Signal

at LAO

Op. mode: Test 1

2

Vpp

911

Vdc(NCOS) Neg. Cosine Sensor DC Signal

at LAO

Op. mode: Test 1

VREF

V

912

dVoff()

Diff. Sine and Cosine Signal

Offsets

dVoff() = V(PSIN) − V(NSIN),

dVoff() = V(PCOS) − V(NCOS)

-50

50

mV

913

VR()

Sine/Cosine AC Signal Ratio

VR() = V(PSIN) / V(PCOS),

VR() = V(NSIN) / V(NCOS)

0.95

1.05