MPC8377E datasheet(17/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR1 and DDR2 SDRAM

Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

Table 15 provides the recommended operating conditions for the DDR SDRAM component(s) when

GVDD(typ) = 2.5 V.

Output low current (VOUT =0.3 V)

IOL

13.4

—

Note:

1 GV

DD is expected to be within 50 mV of the DRAM GVDD at all times.

2 MV

REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3 V

TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4 Output leakage is measured with all outputs disabled, 0 V

≤ V

OUT ≤ GVDD.

5 See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 14. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V

Parameter

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

CIO

Delta input/output capacitance: DQ, DQS, DQS

CDIO

—0.5

Note:

1 This parameter is sampled. GV

DD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 15. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V

Parameter

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

2.375

2.625

I/O reference voltage

MVREF

0.49

× GV

0.51

× GV

V2, 5

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

Input high voltage

VIH

MVREF + 0.18

GVDD + 0.3

—

Input low voltage

VIL

–0.3

MVREF – 0.18

—

Output leakage current

IOZ

–40

μA4

Output high current (VOUT = 1.9 V)

IOH

–15.2

—

Output low current (VOUT = 0.38 V)

IOL

15.2

—

Note:

1 GV

DD is expected to be within 50 mV of the DRAM GVDD at all times.

2 MV

REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3 V

TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4 Output leakage is measured with all outputs disabled, 0 V

≤ V

OUT ≤ GVDD.

5 See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)

Parameter

Symbol

Min

Max

Unit

Notes

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