MPC8377E datasheet(108/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

108

Freescale Semiconductor

Clocking

Table 74 provides the operating frequencies for the TePBGA II package under recommended operating

conditions (see Table 3).

PCI Express1, 2

csb_clk/3

Off, csb_clk, csb_clk/2, csb_clk/3

SATA1, 2

csb_clk/3

Off, csb_clk

This only applies to I2C1 (I2C2 clock is not configurable).

Table 74. Operating Frequencies for TePBGA II

Parameter 1

The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting csb_clk,

MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The

value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core, USB

modules, SATA, and eSDHC will not exceed their respective value listed in this table.

Minimum Operating

Frequency (MHz)

Maximum Operating

Frequency (MHz)

e300 core frequency (core_clk)333

800

Coherent system bus frequency (csb_clk)133

400

DDR2 memory bus frequency (MCK) 2

The DDR data rate is 2

× the DDR memory bus frequency.

125

200

DDR1 memory bus frequency (MCK) 2

167

333

Local bus frequency (LCLKn) 3

The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the

csb_clk frequency (depending on RCWLR[LBCM]).

—133

Local bus controller frequency (lbc_clk)—

400

PCI input frequency (CLKIN or PCI_CLK)

eTSEC frequency

—

400

Security encryption controller frequency

—

200

USB controller frequency

—

200

eSDHC controller frequency

—

200

PCI Express controller frequency

—

400

SATA controller frequency

—

200

Note:

Table 73. Configurable Clock Units (continued)

Unit

Default Frequency

Options

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