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L9803 bảng dữ liệu(PDF) 101 Page - STMicroelectronics

tên linh kiện L9803
Giải thích chi tiết về linh kiện  Super smart power motor driver with 8-Bit MCU, RAM, EEPROM, ADC, WDG, Timers, PWM and H-bridge driver
PDF  126 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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L9803 bảng dữ liệu(HTML) 101 Page - STMicroelectronics

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L9803
On-Chip Peripherals
101/126
Figure 47.
EEPROM Block Diagram
5.9.2
Functional description
Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM/RAM location when the E2LAT bit of the CR
register is cleared. The address decoder selects the desired byte. The 8 sense amplifiers
evaluate the stored byte which is put on the data bus.
Write operation (E2LAT=1)
The EEPROM programming flowchart is shown in Figure 49.
To access the write mode, the LAT with E2LAT bit has to be set by software (the E2PGM bit
remains cleared). When a write access to the EEPROM area occurs, the value is latched
inside the 16 data latches according to its address.
When E2PGM bit is set by the software, all the previous bytes written in the data latches (up
to 16) are programmed in the EEPROM cells. The effective high address (row) is
determined by the last EEPROM write sequence. To avoid wrong programming, the user
must take care that all the bytes written between two programming sequences have the
same high address: only the four Least Significant Bits of the address can change.
BUFFER
ROW
DECODER
4*8 BITS
DATA LATCHES
DATA
MULTIPLEXER
HIGH VOLTAGE PUMP
EEPROM
MEMORY
MATRIX
1 ROW = 4 * 8 BITS
ADDRESS
DECODER
ADDRESS
BUS
DATA
BUS
E2ITE E2LAT E2PGM
EEPCR
.
.
.
.
.
.
32
32
8
8
4
4
12
INTERRUPT
REQUEST
FALLING
EDGE
DETECTOR
8 bit
Read amplifiers



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