PSD4235G2-12UT datasheet(22/124 Pages) STMICROELECTRONICS

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PSD register description and address offsets

PSD4235G2V

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PSD register description and address offsets

Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base

address. The CSIOP space is the 256 bytes of address that is allocated by the user to the

internal PSD registers. Table 5 provides brief descriptions of the registers in CSIOP space.

The following sections give a more detailed description.

Table 5.

Port

Other(1)

Description

Data In

Reads Port pin as input, MCU I/O

input mode

Control

Selects mode between MCU I/O or

Address Out

Data Out

Stores data for output to Port pins,

MCU I/O output mode

Direction

Configures Port pin as input or output

Drive Select

Configures Port pins as either CMOS

or Open Drain on some pins, while

selecting high slew rate on other pins.

Input macrocell

Reads input macrocells

Enable Out

Reads the status of the output enable

to the I/O Port driver

Output

macrocells A

READ - reads output of macrocells A

WRITE - loads macrocell Flip-flops

Output

macrocells B

READ - reads output of macrocells B

WRITE - loads macrocell Flip-flops

Mask

macrocells A

Blocks writing to the output macrocells

Mask

macrocells B

Blocks writing to the output macrocells

Flash Memory

Protection

Read only - Primary Flash Sector

Protection

Flash Boot

Protection

Read only - PSD Security and

secondary Flash memory Sector

Protection

JTAG Enable

Enables JTAG Port

PMMR0

Power Management register 0

PMMR2

Power Management register 2

Page

Page register

Places PSD memory areas in

Program and/or Data space on an

individual basis.

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