PSD4235G2-12UT datasheet(80/124 Pages) STMICROELECTRONICS

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I/O ports

PSD4235G2V

80/124

Figure 27.

Peripheral I/O mode

19.9

JTAG in-system programming (ISP)

Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can

multiplex JTAG operations with other functions on Port E because In-System Programming

(ISP) is not performed during normal system operation. For more information on the JTAG

Port, see Figure 33: Reset (RESET) timing.

19.10

MCU Reset mode

Ports F and G can be configured to operate in MCU Reset mode. This mode is available

when PSD is configured for the Motorola 16-bit 683xx and HC16 family and is active only

during reset.

At the rising edge of the Reset input, the MCU reads the logic level on the data bus (D15-

D0) pins. The MCU then configures some of its I/O pin functions according to the logic level

input on the data bus lines. Two dedicated buffers are usually enabled during reset to drive

the data bus lines to the desired logic level.

The PSD can replace the two buffers by configuring Ports F and G to operate in MCU Reset

mode. In this mode, the PSD will drive the pre-defined logic level or data pattern on to the

MCU data bus when Reset is active and there is no ongoing bus cycle. After reset, Ports F

and G return to the normal Data Port mode.

The MCU Reset mode is enabled and configured in PSDsoft Express. The user defines the

logic level (data pattern) that will be drive out from Ports F and G during reset.

PSEL0

PSEL1

PSEL

VM REGISTER BIT 7

PA0 - PA7

D0-D7

DATA BUS

AI02886

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