82G33 datasheet(45/437 Pages) INTEL

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Signal Description

Datasheet

2.8

Clocks, Reset, and Miscellaneous

Signal Name

Type

Description

HPL_CLKINP

HPL_CLKINN

HCSL

Differential Host Clock In: These pins receive a differential

host clock from the external clock synthesizer. This clock is

used by all of the (G)MCH logic that is in the Host clock

domain.

EXP_CLKINP

EXP_CLKINN

HCSL

Differential PCI-Express Clock In: These pins receive a

differential 100 MHZ Serial Reference clock from the external

clock synthesizer. This clock is used to generate the clocks

necessary for the support of PCI-Express and DMI.

DPL_REFCLKINN

DPL_REFCLKINP

HCSL

Display PLL Differential Clock In

RSTINB

HVIN

Reset In: When asserted, this signal will asynchronously

reset the (G)MCH logic. This signal is connected to the

PCIRST# output of the ICH9. All PCI-Express Graphics Attach

output signals and DMI output signals will also tri-state

compliant to PCI Express Rev 1.0 specification.

This input should have a Schmitt trigger to avoid spurious

resets.

This signal is required to be 3.3 V tolerant.

CL_PWROK

I/O

CMOS

CL Power OK: When asserted, CL_PWROK is an indication to

the (G)MCH that 1.25 V VCC_CL power supply (Manageability

well) has been stable for at least 10 us.

EXP_SLR

CMOS

PCI Express* Static Lane Reversal/Form Factor

Selection: (G)MCH’s PCI Express lane numbers are reversed

to differentiate BTX and ATX form factors.

0 = (G)MCH PCI Express lane numbers are reversed (BTX)

1 = Normal operation (ATX)

TCEN

CMOS

TLS Confidentiality Enable. Enable/disable TLS

Confidentiality. This signal has an internal pull-up.

0 = TLS Confidentiality is disabled.

1 = TLS Confidentiality is enabled.

BSEL2

BSEL1

BSEL0

CMOS

Bus Speed Select: At the assertion of PWROK, the value

sampled on these pins determines the expected frequency of

the bus. Theses pins must also be routed to probe points or

to the XDP connector when applicable.

MTYPE

CMOS

Memory Type: This signal determines DDR2 or DDR3 board

0 = DDR3 (82G33 and 82P35 (G)MCH Only)

1 = DDR2

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