82G33 datasheet(11/437 Pages) INTEL

11 / 437 page

Datasheet

9.4.14

INTR—Interrupt Information ................................................... 342

9.4.15

MGNT—Minimum Grant .......................................................... 342

9.4.16

MLAT—Maximum Latency ....................................................... 343

9.4.17

PID—PCI Power Management Capability ID ............................... 343

9.4.18

PC—PCI Power Management Capabilities................................... 344

9.4.19

PMCS—PCI Power Management Control and Status .................... 345

9.4.20

MID—Message Signaled Interrupt Capability ID ......................... 346

9.4.21

MC—Message Signaled Interrupt Message Control ...................... 347

9.4.22

MA—Message Signaled Interrupt Message Address ..................... 348

9.4.23

MAU—Message Signaled Interrupt Message Upper Address .......... 348

9.4.24

MD—Message Signaled Interrupt Message Data ......................... 349

Functional Description ................................................................................... 350

10.1

Host Interface.................................................................................... 350

10.1.1

FSB IOQ Depth ..................................................................... 350

10.1.2

FSB OOQ Depth .................................................................... 350

10.1.3

FSB GTL+ Termination ........................................................... 350

10.1.4

FSB Dynamic Bus Inversion .................................................... 350

10.1.4.1 APIC Cluster Mode Support ...................................... 351

10.2

System Memory Controller................................................................... 352

10.2.1

System Memory Organization Modes ........................................ 352

10.2.2

Single Channel Mode ............................................................. 352

10.2.3

Dual Channel Symmetric Mode................................................ 352

10.2.4

Dual Channel Asymmetric Mode with Intel® Flex Memory Mode

Enabled ............................................................................... 353

10.2.5

System Memory Technology Supported .................................... 354

10.3

PCI Express* ..................................................................................... 355

10.3.1

PCI Express* Architecture....................................................... 355

10.3.2

Transaction Layer.................................................................. 355

10.3.3

Data Link Layer..................................................................... 355

10.3.4

Physical Layer....................................................................... 355

10.4

Intel® Serial Digital Video Output (SDVO) (Intel® 82Q35, 82Q33,

82G33 GMCH Only) ............................................................................ 356

10.4.1

Intel® SDVO Capabilities......................................................... 356

10.4.2

Intel® SDVO Modes................................................................ 357

10.4.3

PCI Express* and Internal Graphics Simultaneous Operation ....... 358

10.4.3.1 Standard PCI Express* Cards and Internal Graphics..... 358

10.4.3.2 Media Expansion Cards (Concurrent SDVO and PCI

Express*) .............................................................. 358

10.5

Integrated Graphics Controller (Intel® 82Q35, 82Q33, 82G33 GMCH Only) . 360

10.5.1

3D Graphics Pipeline .............................................................. 360

10.5.2

3D Engine ............................................................................ 361

10.5.3

Texture Engine ..................................................................... 362

10.5.4

Raster Engine ....................................................................... 362

10.6

Display Interfaces (Intel® 82Q35, 82Q33, 82G33 Only GMCH) .................. 362

10.6.1

Analog Display Port Characteristics .......................................... 363

10.6.1.1 Integrated RAMDAC ................................................ 363

10.6.1.2 Sync Signals .......................................................... 363

10.6.1.3 VESA/VGA Mode ..................................................... 363

10.6.1.4 DDC (Display Data Channel)..................................... 364

10.6.2

Digital Display Interface ......................................................... 364

10.6.2.1 Multiplexed Digital Display Channels – Intel®

SDVOB and Intel® SDVOC ........................................ 364

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