82G33 datasheet(81/437 Pages) INTEL

81 / 437 page

(G)MCH Register Description

Datasheet

4.4.2.2

DMI Configuration Accesses

Accesses to disabled (G)MCH internal devices, bus numbers not claimed by the Host-

PCI Express bridge, or PCI Bus #0 devices not part of the (G)MCH will subtractively

decode to the ICH9 and consequently be forwarded over the DMI via a PCI Express

configuration TLP.

If the Bus Number is zero, the (G)MCH will generate a Type 0 Configuration Cycle TLP

on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the

Host-PCI Express bridge, the (G)MCH will generate a Type 1 Configuration Cycle TLP

on DMI.

The ICH9 routes configurations accesses in a manner similar to the (G)MCH. The ICH9

decodes the configuration TLP and generates a corresponding configuration access.

Accesses targeting a device on PCI Bus #0 may be claimed by an internal device. The

ICH7 compares the non-zero Bus Number with the Secondary Bus Number and

Subordinate Bus Number registers of its P2P bridges to determine if the configuration

access is meant for Primary PCI, or some other downstream PCI bus or PCI Express

link.

Configuration accesses that are forwarded to the ICH9, but remain unclaimed by any

device or bridge will result in a master abort.

4.5

I/O Mapped Registers

The (G)MCH contains two registers that reside in the processor I/O address space −

the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data

(CONFIG_DATA) Register. The Configuration Address Register enables/disables the

configuration space and determines what portion of configuration space is visible

through the Configuration Data window.

4.5.1

CONFIG_ADDRESS—Configuration Address Register

I/O Address:

0CF8h Accessed as a DW

Default Value:

00000000h

Access:

Size:

32 bits

CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or

Word reference will "pass through" the Configuration Address Register and DMI onto

the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus

Number, Device Number, Function Number, and Register Number for which a

subsequent configuration access is intended.

82G33 bảng dữ liệu(PDF) 81 Page - Intel Corporation

82G33 bảng dữ liệu(HTML) 81 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL