82G33 datasheet(41/437 Pages) INTEL

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Signal Description

Datasheet

2.3

System Memory (DDR2/DDR3) Channel B

Interface Signals

Note: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components.

Signal Name

Type

Description

DDR_B_CK_5:0

SSTL-1.8/1.5

SDRAM Differential Clocks

• DDR2: Three per DIMM (5:0)

• DDR3: Two per DIMM (3:0)

DDR_B_CKB_5:0

SSTL-1.8/1.5

SDRAM Inverted Differential Clocks

• DDR2: Three per DIMM (5:0)

• DDR3: Two per DIMM (3:0)

DDR_B_CSB_3:0

SSTL-1.8/1.5

DDR2/DDR3 Chip Select

(1 per Device Rank)

DDR_B_CKE_3:0

SSTL-1.8/1.5

DDR2/DDR3 Clock Enable

(1 per Device Rank)

DDR_B_ODT_2:0

SSTL-1.8/1.5

DDR2/DDR3 Device Rank 2, 1, and 0 On Die

Termination

DDR_B_ODT_3

SSTL-1.8

DDR2 Device Rank 3 On Die Termination

DDR3_B_ODT_3

SSTL-1.5

DDR3 Device Rank 3 On Die Termination

DDR_B_MA_14:0

SSTL-1.8/1.5

DDR2/DDR3 Address Signals 14:0

DDR_B_BS_2:0

SSTL-1.8/1.5

DDR2/DDR3 Bank Select

DDR_B_RASB

SSTL-1.8/1.5

DDR2/DDR3 RAS signal

DDR_B_CASB

SSTL-1.8/1.5

DDR2/DDR3 CAS signal

DDR_B_WEB

SSTL-1.8/1.5

DDR2/DDR3 Write Enable

DDR_B_DQ_63:0

I/O

SSTL-1.8/1.5

DDR2/DDR3 Data Lines

DDR_B_DM_7:0

SSTL-1.8/1.5

DDR2/DDR3 Data Mask

DDR_B_DQS_7:0

I/O

SSTL-1.8/1.5

DDR2/DDR3 Data Strobes

DDR_B_DQSB_7:0

I/O

SSTL-1.8/1.5

DDR2/DDR3 Data Strobe Complements

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