82G33 datasheet(155/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

155

5.2.32

EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A06–A07h

Default Value:

0000h

Access:

RW, RO

Size:

16 bits

See C0DRB0 register.

Bit

Access &

Default

Description

15:10

000000b

Reserved

9:0

000h

Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3):

5.2.33

EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A08–A09h

Default Value:

0000h

Access:

Size:

16 bits

The DRAM Rank Attribute Registers define the page sizes/number of banks to be used

when accessing different ranks. These registers should be left with their default value

(all zeros) for any rank that is unpopulated, as determined by the corresponding

CxDRB registers. Each byte of information in the CxDRA registers describes the page

size of a pair of ranks. Channel and rank map:

Ch0 Rank0, 1:

108h – 109h

Ch0 Rank2, 3:

10Ah – 10Bh

Ch1 Rank0, 1:

188h – 189h

Ch1 Rank2, 3:

18Ah – 18Bh

Bit

Access &

Default

Description

15:8

00h

Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines

DRAM pagesize/number-of-banks for rank1 for given channel.

7:0

00h

Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines

DRAM pagesize/number-of-banks for rank0 for given channel.

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