82G33 datasheet(118/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

118

Datasheet

5.1.35

TOLUD—Top of Low Usable DRAM

B/D/F/Type:

0/0/0/PCI

Address Offset:

B0–B1h

Default Value:

0010h

Access:

RW/L, RO

Size:

16 bits

This 16 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics Memory

and Graphics Stolen Memory are within the DRAM space defined. From the top,

(G)MCH optionally claims 1 to 64 MB of DRAM for internal graphics if enabled 1, 2 MB

of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for

TSEG, if enabled.

Programming Example :

C1DRB3 is set to 4 GB

TSEG is enabled and TSEG size is set to 1 MB

Internal Graphics is enabled and Graphics Mode Select set to 32 MB

GTT Graphics Stolen Memory Size set to 2 MB

BIOS knows the OS requires 1 GB of PCI space.

BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the

system. This 20MB range at the very top of addressable memory space is lost to APIC

and Intel® TXT.

According to the above equation, TOLUD is originally calculated to: 4 GB =

1_0000_0000h

The system memory requirements are: 4GB (max addressable space) – 1 GB (PCI

space) – 35 MB (lost memory) = 3 GB – 35 MB (minimum granularity) = ECB0_0000h

Since ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h,

TOLUD should be programmed to ECBh.

These bits are Intel® TXT lockable.

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