MAC7200 datasheet(118/976 Pages) FREESCALE

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Detailed Signal Descriptions

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

4.3.4

TDI — Test Data In Pin

The TDI pin is a device input for the JTAG port. This serial pin is sampled in the device on the rising edge

of the TCK pin. During and after a system reset, this pin will be configured as an input with an internal

pull-up active on this signal. This pull-up is implemented using active elements, and is approximately

equivalent to a 20KOhm resistor under typical operating conditions.

4.3.5

TDO — Test Data Output Pin

The TDO pin is a device output for the JTAG port. This pin is a three-state test data output pin that is

actively driven in the shift-IR and shift-DR controller states. The pin state changes on the falling edge of

the TCK pin. During and after a system reset, this pin will be configured as an output with maximum slew

rate enabled.

4.3.6

TCK — Test Clock Pin

The TCK pin is a device input for the JTAG port. This pin provides the test clock input to synchronize the

device’s test logic. TCK is independent of the processor clock, and is used only as the reference clock for

the TMS, TDI and TDO pins. During and after a system reset, this pin will be configured as an input with

an internal pull-down active on this signal. This pull-down is implemented using active elements, and is

approximately equivalent to a 20KOhm resistor under typical operating conditions.

4.3.7

TMS — Test Mode Pin

The TMS pin is a device input for the JTAG port. This pin is used to input the test mode to sequence the

TAP controller’s state machine. The pin is sampled on the rising edge of the TCK pin. During and after a

system reset, this pin will be configured as an input with an internal pull-up active on this signal. This

pull-up is implemented using active elements, and is approximately equivalent to a 20KOhm resistor under

typical operating conditions.

4.3.8

PA[0:7] / DATA[0:7] — Port A I/O Pins and external Databus

PA[0] to PA[7] are configurable general purpose input or output pins. They can be independently

configured to provide either high or reduced output drive, and also to enable or disable either a pull-up or

pull-down resistor on the pin. The pin is multiplexed with the external Data bus lines DATA[0] to

DATA[7]. Each pin can be independently configured to wake the system out of low-power mode (DOZE)

when an external signal is applied using the interrupt functionality.

4.3.9

PA[8] / DATA[8] / PCS[4] — Port A I/O Pin, External Databus, and

DSPI_B

PA[8] is a configurable general purpose input or output pin. It can be independently configured to provide

either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on

the pin. The pin is multiplexed in Primary Peripheral mode with the external Data bus line DATA[8]. In

Secondary Peripheral mode, it can be configured as a chip select pin PCS[4] when in Master mode for the

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