MC68HC705MC4MP datasheet(141/180 Pages) FREESCALE

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Core Timer

Ctimer Control and Status Register

General Release Specification

Core Timer

12.3 Ctimer Control and Status Register

The CTCSR contains the timer interrupt flag, the timer interrupt enable

bits, and the real-time interrupt rate select bits. Figure 12-2 shows the

value of each bit in the CTCSR when coming out of reset.

CTOF — Core Timer Overflow Flag

CTOF is a clearable, read-only status bit and is set when the 8-bit

ripple counter rolls over from $FF to $00. A CPU interrupt request will

be generated if CTOIE is set. Clearing the CTOF is done by writing a

0 to it. Writing a 1 to CTOF has no effect on the bit’s value. Reset

clears CTOF.

RTIF — Real-Time Interrupt Flag

The real-time interrupt circuit consists of a four stage divider and a

1-of-4 selector. The clock frequency that drives the RTI circuit is E/213

(or E/8192) with four additional divider stages giving a maximum

interrupt period of four seconds at a crystal frequency of 32.768 kHz.

RTIF is a clearable, read-only status bit and is set when the output of

the chosen (1-of-4 selection) stage goes active. A CPU interrupt

request will be generated if RTIE is set. Clearing the RTIF is done by

writing a 0 to it. Writing a 1 to RTIF has no effect on this bit. Reset

clears RTIF.

CTOIE — Core Timer Overflow Interrupt Enable

When this bit is set, a CPU interrupt request is generated when the

CTOF bit is set. Reset clears this bit.

Address:

$0008

Bit 7

654321

Bit 0

Read:

CTOF

RTIF

CTOIE

RTIE

RT1

RT0

Write:

Reset:

00000011

= Unimplemented

Figure 12-2. Core Timer Control and Status Register (CTCSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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