MC68HC705MC4MP datasheet(26/180 Pages) FREESCALE

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General Description

MC68HC705MC4 — Rev. 2.0

General Description

1.5.7 PD6/TCAP1/TCMP, PD7/TCAP2

These two I/O pins comprise port D and are shared with the 16-bit timer

subsystem. PD7 is always an input. PD6 can be used as an input or

output port if the TCAP1 interrupt is disabled and the TCAP1/TCMP bit

is clear in the TCR. This is the state upon RESET. Writes to PD7 have

no effect. They may be read at any time, regardless of the mode of

operation of the 16-bit timer. Refer to Section 7. Input/Output Ports

and Section 9. 16-Bit Timer.

1.5.8 IRQ/VPP

This pin has two different choices of interrupt triggering sensitivity

through the IRQ (maskable interrupt request) bit in the interrupt status

and control register (ISCR). The choices are:

1. Edge-sensitive triggering only

2. Both edge-sensitive and level-sensitive triggering

In addition, the IRQ pin may be selected to trigger an interrupt on either

the rising or falling edge of the IRQ pin signal through the EDGE bit in

the ISCR.

The MCU completes the current instruction before it responds to the

interrupt request.

If the option is selected to include level-sensitive triggering, the IRQ input

requires an external resistor to V

DD for wire-OR operation.

The IRQ pin contains an internal Schmitt trigger as part of its input to

improve noise immunity. Refer to Section 4. Interrupts.

This pin also is used to supply the MC68HC705MC4 EPROM array with

the programming voltage.

NOTE:

If the voltage level applied to the IRQ pin exceeds VDD, it can affect the

MCU’s mode of operation. See Section 6. Operating Modes.

Freescale Semiconductor, Inc.

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