MC68HC705MC4MP datasheet(135/180 Pages) FREESCALE

tên linh kiện	MC68HC705MC4MP

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Serial Communications Interface

SCI I/O Registers

General Release Specification

Serial Communications Interface

FE — Receiver Framing Error

This clearable, read-only flag is set when there is a logic 0 where a

stop bit should be in the character shifted into the receive shift

overrun error, the OR bit is set and the FE bit is not set. Clear the FE

bit by reading the SCSR, and then reading the SCDR. Reset clears

the FE bit.

1 = Framing error

0 = No framing error

11.6.5 Baud Rate Register

The baud rate register selects the baud rate for both the receiver and the

transmitter.

SCP1 and SCP0 — SCI Prescaler Select Bits

These read/write bits control prescaling of the baud rate generator

clock, as shown in Table 11-1. Resets clear both SCP1 and SCP0.

Address:

$000A

Bit 7

654321

Bit 0

Read:

SCP1

SCP0

SCR2

SCR1

SCR0

Write:

Reset:

UUUU

= Unimplemented

U = Unaffected

Figure 11-8. Baud Rate Register (BAUD)

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