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UJA1075TW/5V0/WD bảng dữ liệu(PDF) 11 Page - NXP Semiconductors

tên linh kiện UJA1075TW/5V0/WD
Giải thích chi tiết về linh kiện  High-speed CAN/LIN core system basis chip
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UJA1075_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 May 2010
11 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
6.2.2 Register map
The first three bits (A2, A1 and A0) of the message header define the register address.
The fourth bit (RO) defines the selected register as read/write or read only.
Fig 4.
SPI timing protocol
SCS
SCK
01
sampled
floating
floating
mce634
X
X
MSB
14
13
12
01
LSB
MSB
14
13
12
01
LSB
X
SDI
SDO
02
03
04
15
16
Table 3.
Register map
Address bits 15, 14 and 13
Write access bit 12 = 0
Read/Write access bits 11... 0
000
0 = read/write, 1 = read only
WD_and_Status register
001
0 = read/write, 1 = read only
Mode_Control register
010
0 = read/write, 1 = read only
Int_Control register
011
0 = read/write, 1 = read only
Int_Status register



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