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UJA1075TW/5V0/WD bảng dữ liệu(PDF) 42 Page - NXP Semiconductors |
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UJA1075TW/5V0/WD bảng dữ liệu(HTML) 42 Page - NXP Semiconductors |
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42 / 53 page  UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 May 2010 42 of 53 NXP Semiconductors UJA1075 High-speed CAN/LIN core system basis chip [1] . Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 18. [2] Bus load conditions are: CL = 1 nF and RL =1kΩ; CL = 6.8 nF and RL = 660 Ω; CL = 10 nF and RL = 500 Ω. [3] . Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 18. [4] tPD(RX)sym =tPD(RX)r − tPD(RX)f. [5] A system reset will be performed if the watchdog is in Window mode and is triggered less than ttrig(wd)1 after the start of the watchdog period (or in the first half of the watchdog period). [6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4); valid in watchdog Window mode only. δ3 duty cycle 3 Vth(rec)RX(max) = 0.778VBAT Vth(dom)RX(max) = 0.616VBAT tbit = 96 μs; VBAT = 7 V to 18 V; LSC = 1 [1] [2] 0.417 - - Vth(rec)RX(max) = 0.797VBAT Vth(dom)RX(max) = 0.630VBAT tbit = 96 μs; VBAT = 5.5V to 7V; LSC=1 [1] [2] 0.417 - - δ4 duty cycle 4 Vth(rec)RX(min) = 0.389VBAT Vth(dom)RX(min) = 0.251VBAT; tbit = 96 μs VBAT = 7.6 V to 18 V; LSC = 1 [2] [3] - - 0.590 Vth(rec)RX(min) = 0.378VBAT Vth(dom)RX(min) = 0.242VBAT; tbit = 96 μs VBAT = 6.1 V to 7.6V; LSC = 1 [2] [3] - - 0.590 tPD(RX)r rising receiver propagation delay VBAT = 5.5 V to 18 V; RRXDL = 2.4 kΩ CRXDL = 20 pF -- 6 μs tPD(RX)f falling receiver propagation delay VBAT = 5.5 V to 18 V; RRXDL = 2.4 kΩ CRXDL = 20 pF -- 6 μs tPD(RX)sym receiver propagation delay symmetry VBAT = 5.5 V to 18 V; RRXDL = 2.4 kΩ CRXDL = 20 pF [4] −2- +2 μs twake(busdom)min minimum bus dominant wake-up time 28 - 104 μs tto(dom)TXDL TXDL dominant time-out time LIN online mode; VTXDL = 0 V 20 - 80 ms Wake bias output; pin WBIAS tWBIASL WBIAS LOW time 227 - 278 μs tcy cycle time WBC = 1 58.1 - 71.2 ms WBC = 0 14.5 - 17.8 ms Watchdog ttrig(wd)1 watchdog trigger time 1 Normal mode watchdog Window mode only [5] 0.45 × NWP[6] - 0.555 × NWP[6] ms ttrig(wd)2 watchdog trigger time 2 Normal, Standby and Sleep modes watchdog Window mode only [7] 0.9 × NWP[6] -1.11 × NWP[6] ms Oscillator fosc oscillator frequency 460.8 512 563.2 kHz Table 11. Dynamic characteristics …continued Tvj = −40 °C to +150 °C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; RLIN =500 Ω; R(CANH- CANL) = 45 Ω to 65 Ω; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit δ1 δ3 , t bus rec () min () 2t bit × ------------------------------- = δ2 δ4 , t bus rec () max () 2t bit × -------------------------------- = |
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