UJA1075TWSLASH5V0SLASHWD datasheet(20/53 Pages) NXP

20 / 53 page

UJA1075_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

20 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

6.6 Power supplies

6.6.1 Battery pin (BAT)

The SBC contains a single supply pin, BAT. An external diode is needed in series to

protect the device against negative voltages. The operating range is from 4.5 V to 28 V.

The SBC can handle maximum voltages up to 40 V.

If the voltage on pin BAT falls below the power-off detection threshold, Vth(det)poff, the SBC

immediately enters Off mode, which means that the voltage regulators and the internal

logic are shut down. The SBC leaves Off mode for Standby mode as soon as the voltage

rises above the power-on detection threshold, Vth(det)pon. The POSI bit in the Int_Status

6.6.2 Voltage regulator V1

Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional

transceivers. V1 is supplied by pin BAT and delivers up to 250 mA at 3.3 V or 5 V

(depending on the UJA1075 version).

To prevent the device overheating at high ambient temperatures or high average currents,

an external PNP transistor can be connected as illustrated in Figure 6. In this

configuration, the power dissipation is distributed between the SBC and the PNP

transistor. Bit PDC in the Mode_Control register (Table 5) is used to regulate how the

power dissipation is distributed

− if PDC = 0, the PNP transistor will be activated when the

load current reaches 85 mA (50 mA if PDC = 1) at Tvj =150 °C. V1 will continue to deliver

85 mA while the transistor delivers the additional load current (see Figure 7 and Figure 8).

Fig 6.

External PNP transistor control circuit

UJA107x

VEXCTRL

VEXCC

015aaa098

BAT

battery

UJA1075TW/5V0/WD bảng dữ liệu(PDF) 20 Page - NXP Semiconductors