PPC5125YVN400 datasheet(52/92 Pages) FREESCALE

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MPC5125 Microcontroller Data Sheet, Rev. 3

Electrical and Thermal Characteristics

Freescale Semiconductor

4.3.5.3

DDR2 SDRAM AC Timing Specifications

Address and control output hold time

relative to MCK rising edge

tOH(base)

tCK/2 – 1000

—

2,3

A5.7

DQ and DM output setup time relative to

DQS

tDS1(base)

tCK/4 – 750

—

2,3

A5.8

DQ and DM output hold time relative to

DQS

tDH1(base)

tCK/4 – 750

—

2,3

A5.9

DQS-DQ skew for DQS and associated

DQ inputs

tDQSQ

– (tCK/4 – 600)

tCK/4 – 600

A5.10

DQS window position related to CAS

read command

tDQSEN

2tCK – 500

3tCK – 1000

ps 1,2,3,4,5 A5.11

NOTES:

1 Measured with clock pin loaded with differential 100

Ω termination resistor.

2 Measured with all outputs except the clock loaded with 50

Ω termination resistor to V

DD_IO_MEM/2.

3 All transitions measured at mid-supply (V

DD_IO_MEM/2).

4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.

5 The window position is given for t

DQSEN = 2.0 tCK (RDLY = 2, HALF DQS DLY = QUART DQS DLY = 0) with CL = 3

MobileDDR/LPDDR SDRAM device. For other values of tDQSEN, the window position is shifted accordingly.

Table 23. DDR2 (DDR2-400) SDRAM Timing Specifications

At recommended operating conditions with VDD_IO_MEM of ±5%

Parameter

Symbol

Min

Max

Unit Notes SpecID

Clock cycle time, CL = x

tCK

5000

—

A5.1

MCK AC differential crosspoint voltage

VOX-AC (VDD_IO_MEM × 0.5) – 0.1 (VDD_IO_MEM × 0.5) + 0.1 V

A5.2

CK HIGH pulse width

tCH

0.47

0.53

tCK

1,3

A5.3

CK LOW pulse width

tCL

0.47

0.53

tCK

1,3

A5.4

Skew between MCK and DQS transitions

tDQSS

−0.25

0.25

tCK

2,3

A5.5

Address and control output setup time

relative to MCK rising edge

tOS(base)

tCK/2 − 750

—

2,3

A5.6

Address and control output hold time

relative to MCK rising edge

tOH(base)

tCK/2 − 750

—

2,3

A5.7

DQ and DM output setup time relative to

DQS

tDS1(base)

tCK/4 − 500

—

2,3

A5.8

DQ and DM output hold time relative to

DQS

tDH1(base)

tCK/4 − 500

—

2,3

A5.9

DQS-DQ skew for DQS and associated

DQ inputs

tDQSQ

– (tCK/4 – 600)

tCK/4 − 600

A5.10

DQS window position related to CAS

read command

tDQSEN

2.5tCK

3tCK + 1500

1,2,3,4,

A5.11

Table 22. MobileDDR/LPDDR SDRAM Timing Specifications (continued)

At recommended operating conditions with VDD_IO_MEM of ±5%

Parameter

Symbol

Min

Max

Unit Notes SpecID

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