PPC5125YVN400 datasheet(33/92 Pages) FREESCALE

33 / 92 page

TMS

—

ALT0

ALT1

ALT2

ALT3

TMS

—

JTAG

—

VDD_IO

3. This JTAG pin has an

internal pullup P-FET, and

cannot be configured.

D15

TRST

—ALT0

ALT1

ALT2

ALT3

TRST

—

JTAG

—

VDD_IO

3. This JTAG pin has an

internal pullup P-FET, and

cannot be configured.

D16

System Control

HRESET

—ALT0

ALT1

ALT2

ALT3

HRESET

—

VDD_IO

1. This pin is an input or

open-drain output, and have

internal pull-up P-FETs. This

pin can not be configured.

5. This pin contains an

enabled internal

schmitt-trigger.

A17

PORESET

—ALT0

ALT1

ALT2

ALT3

PORESET

—

VDD_IO

1. This pin is an input or

open-drain output, and have

internal pull-up P-FETs. This

pin can not be configured.

2. This pin is an input only.

This pin cannot be configured.

5. This pin contains an

enabled internal

schmitt-trigger.

C17

SRESET

—ALT0

ALT1

ALT2

ALT3

SRESET

—

VDD_IO

1. This pin is an input or

open-drain output, and have

internal pull-up P-FETs. This

pin can not be configured.

5. This pin contains an

enabled internal

schmitt-trigger.

A18

Table 2. MPC5125 Pin Multiplexing (continued)

Pad I/O

Control

Register1

and Offset2

Alternate

Function3

Functions4

Peripheral5

I/O

Direction

Power Domain

Notes

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