PIC18F23K20-ESLASHML datasheet(160/456 Pages) MICROCHIP

160 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 160

 2010 Microchip Technology Inc.

13.1

Timer1 Operation

Timer1 can operate in one of the following modes:

•Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR1CS of the T1CON register. When TMR1CS is

cleared (= 0), Timer1 increments on every internal

instruction cycle (FOSC/4). When the bit is set, Timer1

increments on every rising edge of either the Timer1

external clock input or the Timer1 oscillator, if enabled.

When the Timer1 oscillator is enabled, the digital

circuitry

associated

with

the

RC1/T1OSI

and

RC0/T1OSO/T13CKI pins is disabled. This means the

values of TRISC<1:0> are ignored and the pins are

read as ‘0’.

FIGURE 13-1:

TIMER1 BLOCK DIAGRAM

FIGURE 13-2:

TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

On/Off

Prescaler

1, 2, 4, 8

Synchronize

Detect

T1OSO/T13CKI

T1OSI

TMR1ON

TMR1L

Set

TMR1IF

on Overflow

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer1

Timer1 Clock Input

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

T1OSO/T13CKI

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR1L

Internal Data Bus

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

Read TMR1L

Write TMR1L

TMR1ON

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

On/Off

Timer1

Timer1 Clock Input

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