PIC18F23K20-ESLASHML datasheet(33/456 Pages) MICROCHIP

33 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 33

PIC18F2XK20/4XK20

2.5.2.1

OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the TUN<5:0> bits of

the OSCTUNE register (Register 2-2).

The default value of the TUN<5:0> is ‘000000’. The

value is a 6-bit two’s complement number.

When

the

OSCTUNE

modified,

the

HFINTOSC frequency will begin shifting to the new

frequency. Code execution continues during this shift.

There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Mon-

itor (FSCM) and peripherals, are not affected by the

change in frequency.

The OSCTUNE register also implements the INTSRC

and PLLEN bits, which control certain features of the

internal oscillator block.

The INTSRC bit allows users to select which internal

oscillator provides the clock source when the 31 kHz

frequency option is selected. This is covered in greater

detail in Section 2.2.3 “Low Frequency Selection”.

The PLLEN bit controls the operation of the frequency

multiplier, PLL, in internal oscillator modes. For more

details about the function of the PLLEN bit see

Section 2.6.2 “PLL in HFINTOSC Modes”

OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0

INTSRC

PLLEN(1)

TUN5

TUN4

TUN3

TUN2

TUN1

TUN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

INTSRC: Internal Oscillator Low-Frequency Source Select bit

= 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)

= 31 kHz device clock derived directly from LFINTOSC internal oscillator

bit 6

PLLEN: Frequency Multiplier PLL for HFINTOSC Enable bit(1)

= PLL enabled for HFINTOSC (8 MHz and 16 MHz only)

= PLL disabled

bit 5-0

TUN<5:0>: Frequency Tuning bits

011111

= Maximum frequency

011110

• • •

000001

000000

= Oscillator module is running at the factory calibrated frequency.

111111

• • •

100000

= Minimum frequency

Note 1:

The PLLEN bit is active only when the HFINTOSC is the primary clock source (FOSC<2:0> = 100X) and

the selected frequency is 8 MHz or 16 MHz. Otherwise, the PLLEN bit is unavailable and always reads ‘0’.

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