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10HSI-S008-R0-C bảng dữ liệu(PDF) 58 Page - Hirose Electric |
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10HSI-S008-R0-C bảng dữ liệu(HTML) 58 Page - Hirose Electric |
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58 / 71 page ![]() Signal Integrity Report – IT3 (32mm) Page 58 The total single-ended cross-talk values in % at 120ps (20% to 80%) rise time and 2.625GHz bandwidth for port 15 is shown in Figure 96. Figure 96 Single-ended cross-talk (in %) from simulations for port 15 and step input @ 120ps (20% to 80%) rise time and 2.625GHz BW 4.2.5 System Voltage and Timing Margins To demonstrate the IT3’s performance for single-ended signals, we ran simulations for the following setup: Ideal voltage source with package via. Center pin of IT3 connector with via transition in the 16th PCB routing layer. 152.4mm (6 inches) PCB trace from driver to IT3 connector, and 152.4mm (6 inches) PCB trace from IT3 connector to receiver, including via transition to the receiver. Note: Since the time steps used for the simulations were of 1ps, the timing jitter values have an error margin of 1ps. The eye height is defined as the absolute maximum eye opening. |
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