TMP320C6720RFP300 datasheet(14/118 Pages) TI

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TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

www.ti.com

Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7

contains a description of the bits.

Reserved

CSPRST

R/W, 1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024)

Table 2-7. CFGBRIDGE Register Bit Field Description (0x4000 0024)

BIT NO.

NAME

RESET VALUE

READ WRITE

DESCRIPTION

31:1

Reserved

N/A

Reads are indeterminate. Only 0s should be written to these bits.

CSPRST

R/W

Resets the CSP Bridge (BR2 in Figure 2-4).

1 = Bridge Reset Asserted

0 = Bridge Reset Released

CAUTION

The CSPRST bit must be asserted after any change to the PLL that affects SYSCLK1

and SYSCLK2 and must be released before any accesses to the CSP bridge occur

from either the dMAX or the UHPI.

Device Overview

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