TMP320C6720RFP300 datasheet(51/118 Pages) TI

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TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-9. EMIF Asynchronous Interface Timing Requirements(1)(2)

NO.

MIN

MAX UNIT

Input setup time, read data valid on EM_D[31:0] before EM_CLK

tsu(EM_DV-EM_CLKH)A

rising

th(EM_CLKH-EM_DIV)A

Input hold time, read data valid on EM_D[31:0] after EM_CLK rising

tsu(EM_CLKH-EM_WAITV)A

Setup time, EM_WAIT valid before EM_CLK rising edge

th(EM_CLKH-EM_WAITIV)A

Hold time, EM_WAIT valid after EM_CLK rising edge

tw(EM_WAIT)A

Pulse width of EM_WAIT assertion and deassertion

2E + 5

Delay from EM_WAIT sampled deasserted on EM_CLK rising to

td(EM_WAITD-HOLD)A

4E(3)

beginning of HOLD phase

Setup before end of STROBE phase (if no extended wait states are

tsu(EM_WAITA-HOLD)A

inserted) by which EM_WAIT must be sampled asserted on

4E(3)

EM_CLK rising in order to add extended wait states.(4)

(1)

E = SYSCLK3 (EM_CLK) period.

(2)

These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.

(3)

These parameters specify the number of EM_CLK cycles of latency between EM_WAIT being sampled at the device pin and the EMIF

entering the HOLD phase. However, the asynchronous setup (parameter 30) and hold time (parameter 31) around each EM_CLK edge

must also be met in order to ensure the EM_WAIT signal is correctly sampled.

(4)

In Figure 4-13, it appears that there are more than 4 EM_CLK cycles encompassed by parameter 35. However, EM_CLK cycles that are

part of the extended wait period should not be counted; the 4 EM_CLK requirement is to the start of where the HOLD phase would

begin if there were no extended wait cycles.

Table 4-10. EMIF Asynchronous Interface Switching Characteristics(1)

NO.

PARAMETER

MIN

MAX UNIT

100-MHz EMIF Frequency

tc(EM_CLK)

Cycle time, EMIF clock EM_CLK

133-MHz EMIF Frequency

7.5

tw(EM_CLK)

Pulse width, high or low, EMIF clock EM_CLK

tdis(EM_CLKH-EM_DHZ)S

Delay time, EM_CLK rising to EM_D[31:0] 3-stated

7.7

tena(EM_CLKH-EM_DLZ)S

Output hold time, EM_CLK rising to EM_D[31:0] driving

1.15

td(EM_CLKH-EM_CS2V)A

Delay time, from EM_CLK rising edge to EM_CS[2] valid

td(EM_CLKH-EM_WE_DQMV)A

Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid

td(EM_CLKH-EM_AV)A

Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid

td(EM_CLKH-EM_DV)A

Delay time, EM_CLK rising to EM_D[31:0] valid

td(EM_CLKH-EM_OEV)A

Delay time, EM_CLK rising to EM_OE valid

td(EM_CLKH-EM_RW)A

Delay time, EM_CLK rising to EM_RW valid

tdis(EM_CLKH-EM_DDIS)A

Delay time, EM_CLK rising to EM_D[31:0] 3-stated

td(EM_CLKH-EM_WE)A

Delay time, EM_CLK rising to EM_WE valid

(1)

These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.

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