TMP320C6720RFP300 datasheet(105/118 Pages) TI

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BOARD

DVDD (3.3 V)

EMI

Filter

10 mF

0.1 mF

PLLHV

Place Filter and Capacitors as Close

to DSP as Possible

EMI Filter: TDK ACF451832−333, −223, −153, or −103,

Panasonic EXCCET103U, or Equivalent

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

www.ti.com

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-42. Allowed PLL Operating Conditions

ALLOWED SETTING OR RANGE

PARAMETER

DEFAULT VALUE

MIN

MAX

PLLRST = 1 assertion time during initialization

N/A

125 ns

Lock time before setting PLLEN = 1. After changing D0, PLLM, or

N/A

187.5 µs

input clock.

PLL input frequency (PLLREF after D0(1))

12 MHz

50 MHz

PLL multiplier values (PLLM)

x13

x25

PLL output frequency (PLLOUT before dividers D1, D2, D3)(2)

N/A

140 MHz

600 MHz

SYSCLK1 frequency (set by PLLM and dividers D0, D1)

PLLOUT/1

Device Frequency

Specification

SYSCLK2 frequency (set by PLLM and dividers D0, D2)

PLLOUT/2

/2, /3, or /4 of SYSCLK1

SYSCLK3 frequency (set by PLLM and dividers D0, D3)

PLLOUT/3

EMIF Frequency

Specification

(1)

Some values for the D0 divider produce results outside of this range and should not be selected.

(2)

In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter.

CAUTION

SYSCLK1, SYSCLK2, SYSCLK3 must be configured as aligned by setting ALNCTL[2:0]

to '1'; and the PLLCMD.GOSET bit must be written every time the dividers D1, D2, and

D3 are changed in order to make sure the change takes effect and preserves

alignment.

CAUTION

When changing the PLL parameters which affect the SYSCLK1, SYSCLK2, SYSCLK3

dividers, the bridge BR2 in Figure 2-4 must be reset by the CFGBRIDGE register. See

Table 2-7.

The PLL is an analog circuit and is sensitive to power supply noise. Therefore it has a dedicated 3.3-V

power pin (PLLHV) that should be connected to DVDD at the board level through an external filter, as

illustrated in Figure 4-44.

Figure 4-44. PLL Power Supply Filter

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Peripheral and Electrical Specifications

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