MPC5121E datasheet(17/86 Pages) FREESCALE

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Pin Assignments

MPC5121E/MPC5123 Data Sheet, Rev. 4

Freescale Semiconductor

1) This pin is an input or open-drain output. This pin can not be configured. There is an internal pull-up resistor implemented.

2) This pin is an input only. This pin can not be configured.

3) These JTAG pins have internal pull-up P-FETs. This pin can not be configured.

4) This pins should have an external pull-up resistor. Follow PCI specification and see System Design Information.

5) This test pin must be tied to VSS.

6) This pin contains an enabled internal Schmitt trigger.

NOTE

This table indicates only the pins with permananently enabled internal pull-up, pull-down,

or Schmitt trigger. Most of the digital I/O pins can be configured to enable internal pull-up,

pull-down, or Schmitt trigger. See the MPC5121e Microcontroller Reference Manual, IO

Control chapter.

USB_VDDA_BIAS

D22

Analog Power

—

USB_VSSA

C22, E20, E21

Analog Ground

—

USB_VDDA

C21, D20

Analog Power

—

Power and Ground Supplies (SATA PHY)

SATA_RESREF

Analog Power

—

SATA_VDDA_3P3

Analog Power

—

SATA_VDDA_1P2

C5, D1, E2

Analog Power

—

SATA_VDDA_VREG

Analog Power

—

SATA_PLL_VDDA1P2

Analog Power

—

SATA_PLL_VSSA

Analog Ground

—

SATA_RX_VSSA

A6, B4

Analog Ground

—

SATA_TX_VSSA

Analog Ground

—

Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 12 of 12)

Signal

Package Pin Number

Pad Type

Power Supply

Notes

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