MPC5121E datasheet(64/86 Pages) FREESCALE

64 / 86 page

MPC5121E/MPC5123 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

3.3.16

SPDIF

The Sony/Philips Digital Interface (SPDIF) timing is totally asynchronous, therefore there is no need for relationship with the

clock.

3.3.17

CAN

The CAN functions are available as TX and CAN3/4_RX pins at normal IO pads and as CAN1/2 RX pins at the VBAT_RTC

domain. There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.

3.3.18

I2C

This section specifies the timing parameters of the Inter-Integrated Circuit (I2C) interface. Refere to the I2C Bus Specification.

Table 39. I2C Input Timing Specifications – SCL and SDA

Sym

Description

Min

Max

Units

SpecID

Start condition hold time

—

IP-Bus Cycle1

1 Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.

A18.1

Clock low time

—

IP-Bus Cycle1

A18.2

Data hold time

0.0

—

A18.3

Clock high time

—

IP-Bus Cycle1

A18.4

Data setup time

0.0

—

A18.5

Start condition setup time (for repeated start condition only)

—

IP-Bus Cycle1

A18.6

Stop condition setup time

—

IP-Bus Cycle1

A18.7

Table 40. I2C Output Timing Specifications – SCL and SDA

Sym

Description

Min

Max

Units

SpecID

1 Programming IFDR with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to

scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and

division values programmed in IFDR.

Start condition hold time

—

IP-Bus Cycle2

2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA

takes to reach a high level depends on external signal capacitance and pull-up resistor values.

A18.8

Clock low time

—

IP-Bus Cycle2

A18.9

3 Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.

SCL/SDA rise time

—

7.9

A18.10

Data hold time

—

IP-Bus Cycle2

A18.11

SCL/SDA fall time

—

7.9

A18.12

Clock high time

—

IP-Bus Cycle2

A18.13

Data setup time

—

IP-Bus Cycle2

A18.14

Start condition setup time (for repeated start condition only)

—

IP-Bus Cycle2

A18.15

Stop condition setup time

—

IP-Bus Cycle2

A18.16

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