MPC5121E datasheet(35/86 Pages) FREESCALE

35 / 86 page

Electrical and Thermal Characteristics

MPC5121E/MPC5123 Data Sheet, Rev. 4

Freescale Semiconductor

Figure 12. PCI CLK Waveform

Table 21. PCI CLK Specifications

Sym

Description

66 MHz1

1 In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK

requirements vary depending upon whether the clock frequency is above 33 MHz.

33 MHz

Units

SpecID

Min2

2 Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met

across the minimum peak-to-peak portion of the clock waveform as shown in Figure 12.

Max

Min

Max

tcyc

PCI CLK Cycle Time1,3

3 The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system

jitter.

—

A6.1

thigh

PCI CLK High Time

—

A6.2

tlow

PCI CLK Low Time

—

A6.3

—

PCI CLK Slew Rate2

1.5

V/ns

A6.4

Table 22. PCI Timing Parameters1

1 See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven

signal transitions drive to their Voh or Vol level within one Tcyc.

Sym

Description

66 MHz

33 MHz

Units

SpecID

Min2

2 Minimum times are measured at the package pin with the load circuit, and maximum times are measured

with the load circuit as shown in the PCI Local Bus Specification.

Max

Min

Max

tval

CLK to Signal Valid Delay –

bused signals1,2,3

262

A6.5

tval(ptp) CLK to Signal Valid Delay – point

to point1,2,3

262

A6.6

ton

Float to Active Delay1

2—2—

A6.7

toff

Active to Float Delay1

A6.8

tsu

Input Setup Time to CLK – bused

signals3,4

3—7—

A6.9

tsu(ptp) Input Setup Time to CLK – point

to point3,4

3 REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#

and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.

—

10,12

—

A6.10

Input Hold Time from CLK4

0—0—

A6.11

tcyc

PCI CLK

tlow

thigh

0.4Vcc

0.4Vcc, p-to-p

0.3Vcc

0.5Vcc

0.6Vcc

0.2Vcc

(minimum)

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