ATmega64A datasheet(264/392 Pages) ATMEL

264 / 392 page

264

8160C–AVR–07/09

ATmega64A

Figure 25-4. General Port Pin Schematic Diagram

25.5.2

Boundary-scan and the Two-wire Interface

The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-

chain; Two-wire Interface Enable – TWIEN. As shown in Figure 25-5, the TWIEN signal enables

a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general

scan cell as shown in Figure 25-9 is attached to the TWIEN signal.

Note:

1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan

support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in

the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-

scan.

2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to

drive contention.

CLK

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx:

WRITE DDRx

WPx:

WRITE PORTx

RRx:

READ PORTx REGISTER

RPx:

READ PORTx PIN

PUD:

PULLUP DISABLE

CLK

I/O CLOCK

RDx:

READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

SLEEP

SLEEP:

SLEEP CONTROL

Pxn

I/O

See Boundary-scan Description

for Details!

PUExn

OCxn

ODxn

IDxn

PUExn:

PULLUP ENABLE for pin Pxn

OCxn:

OUTPUT CONTROL for pin Pxn

ODxn:

OUTPUT DATA to pin Pxn

IDxn:

INPUT DATA from pin Pxn

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