ATmega64A datasheet(70/392 Pages) ATMEL

70 / 392 page

8160C–AVR–07/09

ATmega64A

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

PORTxn } = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01)

or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully

acceptable, as a high-impedant environment will not notice the difference between a strong high

driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to

one to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state({DDxn,

PORTxn} = 0b11) as an intermediate step.

Table 13-1 summarizes the control signals for the pin value.

13.2.2

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 13-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 13-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t

pd,max and tpd,min respectively.

Table 13-1.

Port Pin Configurations

DDxn

PORTxn

PUD

(in SFIOR)

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled low.

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

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