ATmega64A datasheet(144/392 Pages) ATMEL

144 / 392 page

144

8160C–AVR–07/09

ATmega64A

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 16-2. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3

(1)

Note:

1. The synchronization logic on the input pins (T3/T2/T1) is shown in Figure 16-1.

PSR321

Clear

clk

TIMER/COUNTER2 CLOCK SOURCE

CS20

CS21

CS22

clk

TIMER/COUNTER1 CLOCK SOURCE

CS10

CS11

CS12

clk

TIMER/COUNTER3 CLOCK SOURCE

CS30

CS31

CS32

10-BIT T/C PRESCALER

ATmega64A bảng dữ liệu(PDF) 144 Page - ATMEL Corporation