ATmega64A datasheet(146/392 Pages) ATMEL

146 / 392 page

146

8160C–AVR–07/09

ATmega64A

17. 8-bit Timer/Counter2 with PWM

17.1

Features

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse width Modulator (PWM)

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

17.2

Overview

Timer/Counter2 is a general purpose, single-channel, 8-bit Timer/Counter module. A simplified

block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement of

I/O pins, refer to “Pin Configuration” on page 2. CPU accessible I/O Registers, including I/O bits

and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in

the “Register Description” on page 157.

Figure 17-1. 8-bit Timer/Counter Block Diagram

17.2.1

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt

request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag

Timer/Counter

TCNTn

Waveform

Generation

OCn

= 0

Control Logic

= 0xFF

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCRn

TCCRn

Clock Select

Edge

Detector

( From Prescaler )

clkTn

TOP

OCn

(Int.Req.)

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