ATmega64A datasheet(140/392 Pages) ATMEL

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140

8160C–AVR–07/09

ATmega64A

• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector

(see “Interrupts” on page 60) is executed when the TOV1 flag, located in TIFR, is set.

15.11.18 ETIMSK – Extended Timer/Counter Interrupt Mask Register(1)

Note:

1. This register is not available in ATmega103 compatibility mode.

• Bit 7:6 – Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices, these bits

must be set to zero when ETIMSK is written.

• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (see “Interrupts” on page 60) is executed when the ICF3 flag, located in ETIFR, is set.

• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF3A flag, located in

ETIFR, is set.

• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF3B flag, located in

ETIFR, is set.

• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding Interrupt Vector

(see “Interrupts” on page 60) is executed when the TOV3 flag, located in ETIFR, is set.

• Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare C Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF3C flag, located in

ETIFR, is set.

• Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF1C flag, located in

ETIFR, is set.

Bit

7654

3210

(0x7D)

–

TICIE3

OCIE3A

OCIE3B

TOIE3

OCIE3C

OCIE1C

ETIMSK

Read/Write

R/W

Initial Value

0000

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