ATmega1284P datasheet(330/380 Pages) ATMEL

330 / 380 page

330

8059D–AVR–11/09

ATmega1284P

Notes:

1. In ATmega1284P, this parameter is characterized and not 100% tested.

2. Required only for f

SCL > 100 kHz.

3. Cb = capacitance of one bus line in pF.

4. fCK = CPU clock frequency

5. This requirement applies to all ATmega1284P Two-wire Serial Interface operation. Other devices connected to the Two-wire

Serial Bus need only obey the general fSCL requirement.

6. The actual low period generated by the ATmega1284P Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater

than 6 MHz for the low time requirement to be strictly met at f

SCL = 100 kHz.

7. The actual low period generated by the Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be

strictly met for f

SCL > 308 kHz when fCK = 8 MHz. Still, ATmega1284P devices connected to the bus may communicate at full

speed (400 kHz) with other ATmega1284P devices, as well as any other device with a proper t

LOW acceptance margin.

Figure 26-5. 2-wire Serial Bus Timing

tHIGH

High period of the SCL clock

SCL ≤ 100 kHz

4.0

–

µs

SCL > 100 kHz

0.6

–

µs

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

–

µs

SCL > 100 kHz

0.6

–

µs

HD;DAT

Data hold time

fSCL ≤ 100 kHz

3.45

µs

fSCL > 100 kHz

0.9

µs

tSU;DAT

Data setup time

SCL ≤ 100 kHz

250

–

fSCL > 100 kHz

100

–

tSU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

–

µs

SCL > 100 kHz

0.6

–

µs

BUF

Bus free time between a STOP and START

condition

fSCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

1.3

–

µs

Table 26-7.

2-wire Serial Bus Requirements (Continued)

Symbol

Parameter

Condition

Min

Max

Units

tSU;STA

tLOW

tHIGH

tLOW

tof

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

SCL

SDA

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