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ATmega1284P bảng dữ liệu(PDF) 329 Page - ATMEL Corporation

tên linh kiện ATmega1284P
Giải thích chi tiết về linh kiện  8-bit Microcontroller with 128K Bytes In-System Programmable Flash
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ATmega1284P bảng dữ liệu(HTML) 329 Page - ATMEL Corporation

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329
8059D–AVR–11/09
ATmega1284P
Figure 26-4. SPI Interface Timing Requirements (Slave Mode)
26.7
2-wire Serial Interface Characteristics
Table 26-7 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega1284P 2-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 26-5.
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB
LSB
LSB
MSB
...
...
10
11
11
12
13
14
17
15
9
X
16
Table 26-7.
2-wire Serial Bus Requirements
Symbol
Parameter
Condition
Min
Max
Units
V
IL
Input Low-voltage
-0.5
0.3 V
CC
V
V
IH
Input High-voltage
0.7 V
CC
V
CC + 0.5
V
Vhys
(1)
Hysteresis of Schmitt Trigger Inputs
0.05 VCC
(2)
–V
V
OL
(1)
Output Low-voltage
3 mA sink current
0
0.4
V
t
r
(1)
Rise Time for both SDA and SCL
20 + 0.1C
b
(2)(3)
300
ns
tof
(1)
Output Fall Time from VIHmin to VILmax
10 pF < Cb < 400 pF
(3)
20 + 0.1Cb
(2)(3)
250
ns
t
SP
(1)
Spikes Suppressed by Input Filter
0
50(2)
ns
I
i
Input Current each I/O Pin
0.1V
CC < Vi < 0.9VCC
-10
10
µA
Ci
(1)
Capacitance for each I/O Pin
–
10
pF
f
SCL
SCL Clock Frequency
f
CK
(4) > max(16f
SCL, 250kHz)
(5)
0
400
kHz
Rp
Value of Pull-up resistor
f
SCL ≤ 100 kHz
f
SCL > 100 kHz
t
HD;STA
Hold Time (repeated) START Condition
fSCL ≤ 100 kHz
4.0
–
µs
fSCL > 100 kHz
0.6
–
µs
tLOW
Low Period of the SCL Clock
f
SCL ≤ 100 kHz
(6)
4.7
–
µs
fSCL > 100 kHz
(7)
1.3
–
µs
V
CC
0,4V
–
3mA
----------------------------
1000ns
C
b
-------------------
Ω
V
CC
0,4V
–
3mA
----------------------------
300ns
C
b
----------------
Ω



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