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ATmega1284P bảng dữ liệu(PDF) 193 Page - ATMEL Corporation |
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ATmega1284P bảng dữ liệu(HTML) 193 Page - ATMEL Corporation |
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193 / 380 page ![]() 193 8059D–AVR–11/09 ATmega1284P • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). 17.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. Table 17-8. UCPOLn Bit Settings UCPOLn Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge Bit 15 14 13121110 9 8 –––– UBRR[11:8] UBRRHn UBRR[7:0] UBRRLn 76543210 Read/Write RRRR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 00000000 |
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